System Seminar : Integrating a distributed memory computer on a chip: challenges and opportunities
Event details
| Date | 07.01.2013 |
| Hour | 16:15 › 17:30 |
| Speaker | Benoit Dupont de Dinechin, Kalray Corporation |
| Location | |
| Category | Conferences - Seminars |
Abstract
Three architectural approaches for the integration of processors with hundreds of cores into a single chip have been successfully implemented: the general-purpose GPU architecture, as exemplified by the NVIDIA Fermi architecture, the shared memory manycores represented by the Tilera and the Intel MIC architectures and the distributed memory manycores as experimented with the Intel Single Chip Cloud Computer, and now realized by the Kalray MPPA256 manycore processor.
Integrating a distributed memory supercomputer architecture on a chip is primarily motivated by scalability requirements. Accordingly, the Kalray MPPA256 manycore processor implements a distributed memory architecture similar to those of high-end supercomputers, where compute nodes of 17 SMP cores each, and I/O subsystems of 4 SMP cores each, are connected by specialized networks-on-chip.
Based on the experience of designing the Kalray MPPA256 processor and implementing its programming models, we present the new opportunities and challenges brought by the on-chip integration of a distributed memory supercomputer architecture both in hardware and in software.
Biography
Benoit Dupont de Dinechin is currently the Director of Software Development at Kalray (http://www.kalray.eu), a company that manufactures integrated manycore processors for embedded and industrial applications. He is also the Kalray VLIW core main architect, and co-architect of the Kalray Multi Purpose Processing Array (MPPA). Before joining Kalray, Benoit Dupont de Dinechin was in charge of Research and Development in the STMicroelectronics Software, Tools,Services division, with special focus on compiler design, virtual machines for embedded systems, and component-based software development frameworks. He was promoted to STMicroelectronics National Fellow in 2008. Prior to his work at STMicroelectronics, Benoit Dupont de Dinechin held a position at the applied mathematics department of the military branch of the French Atomic Energy Commission (CEA). In this position, he worked part-time at the Cray Research park (Minnesota), where he developed the software pipeliner of the Cray T3D production compilers. Benoit Dupont de Dinechin earned an engineering degree in Radar and Telecommunications from the Ecole Nationale Superieure de l'Aeronautique et de l'Espace (Toulouse, France), and a doctoral degree in computer systems from the University Pierre et Marie Curie (Paris) under the direction of Prof. P. Feautrier. He completed his post-doctoral studies at the McGill university (Montreal, Canada) at the ACAPS laboratory led by Prof. G. R. Gao.
Three architectural approaches for the integration of processors with hundreds of cores into a single chip have been successfully implemented: the general-purpose GPU architecture, as exemplified by the NVIDIA Fermi architecture, the shared memory manycores represented by the Tilera and the Intel MIC architectures and the distributed memory manycores as experimented with the Intel Single Chip Cloud Computer, and now realized by the Kalray MPPA256 manycore processor.
Integrating a distributed memory supercomputer architecture on a chip is primarily motivated by scalability requirements. Accordingly, the Kalray MPPA256 manycore processor implements a distributed memory architecture similar to those of high-end supercomputers, where compute nodes of 17 SMP cores each, and I/O subsystems of 4 SMP cores each, are connected by specialized networks-on-chip.
Based on the experience of designing the Kalray MPPA256 processor and implementing its programming models, we present the new opportunities and challenges brought by the on-chip integration of a distributed memory supercomputer architecture both in hardware and in software.
Biography
Benoit Dupont de Dinechin is currently the Director of Software Development at Kalray (http://www.kalray.eu), a company that manufactures integrated manycore processors for embedded and industrial applications. He is also the Kalray VLIW core main architect, and co-architect of the Kalray Multi Purpose Processing Array (MPPA). Before joining Kalray, Benoit Dupont de Dinechin was in charge of Research and Development in the STMicroelectronics Software, Tools,Services division, with special focus on compiler design, virtual machines for embedded systems, and component-based software development frameworks. He was promoted to STMicroelectronics National Fellow in 2008. Prior to his work at STMicroelectronics, Benoit Dupont de Dinechin held a position at the applied mathematics department of the military branch of the French Atomic Energy Commission (CEA). In this position, he worked part-time at the Cray Research park (Minnesota), where he developed the software pipeliner of the Cray T3D production compilers. Benoit Dupont de Dinechin earned an engineering degree in Radar and Telecommunications from the Ecole Nationale Superieure de l'Aeronautique et de l'Espace (Toulouse, France), and a doctoral degree in computer systems from the University Pierre et Marie Curie (Paris) under the direction of Prof. P. Feautrier. He completed his post-doctoral studies at the McGill university (Montreal, Canada) at the ACAPS laboratory led by Prof. G. R. Gao.
Links
Practical information
- General public
- Free
Organizer
Contact
- Simone Muller