System Seminars : Exascale Computing: Challenges and Opportunities
Event details
| Date | 20.02.2012 |
| Hour | 13:00 › 14:30 |
| Speaker | Prof. Nader Bagherzadeh, University of California - Irvine, USA (EECS Department) |
| Location | |
| Category | Conferences - Seminars |
Abstract :
This talk gives an overview of current efforts to develop the next generation HPC technologies in order to reach the peak computing power that is more than 100 times faster than the fastest machine of 2011 from Japan. In order to meet this level of improvement, many new hardware and software technologies must be developed to overcome current technological barriers. One key area is to improve power efficiency for the exascale architecture which is planned for 2020. The power efficiency requirements are not unlike what has been taking place for embedded systems. Many architectural concepts from embedded systems may have to be revisited for HPS, including heterogeneous computing and data movement efficiency.
Bio :
Nader Bagherzadeh is a professor of computer engineering in the department of electrical engineering and computer science at the University of California, Irvine, where he served as a chair from 1998 to 2003. Dr Bagherzadeh has been involved in research and development in the areas of:
computer architecture, reconfigurable computing, VLSI chip design, network-on-chip, sensor networks, and computer graphics since he received a Ph.D. degree from the University of Texas at Austin in 1987.
Professor Bagherzadeh has published more than 200 articles in peer-reviewed journals and conferences. He has trained hundreds of students who have assumed key positions in software and computer systems design companies in the past twenty years. He has been a PI or Co-PI on more than 4 million dollars worth of research grants for developing next generation computer systems for applications in general purpose computing and digital signal processing.
This talk gives an overview of current efforts to develop the next generation HPC technologies in order to reach the peak computing power that is more than 100 times faster than the fastest machine of 2011 from Japan. In order to meet this level of improvement, many new hardware and software technologies must be developed to overcome current technological barriers. One key area is to improve power efficiency for the exascale architecture which is planned for 2020. The power efficiency requirements are not unlike what has been taking place for embedded systems. Many architectural concepts from embedded systems may have to be revisited for HPS, including heterogeneous computing and data movement efficiency.
Bio :
Nader Bagherzadeh is a professor of computer engineering in the department of electrical engineering and computer science at the University of California, Irvine, where he served as a chair from 1998 to 2003. Dr Bagherzadeh has been involved in research and development in the areas of:
computer architecture, reconfigurable computing, VLSI chip design, network-on-chip, sensor networks, and computer graphics since he received a Ph.D. degree from the University of Texas at Austin in 1987.
Professor Bagherzadeh has published more than 200 articles in peer-reviewed journals and conferences. He has trained hundreds of students who have assumed key positions in software and computer systems design companies in the past twenty years. He has been a PI or Co-PI on more than 4 million dollars worth of research grants for developing next generation computer systems for applications in general purpose computing and digital signal processing.
Practical information
- General public
- Free