System Seminars - Title : Scalable Memory Hierarchies with QoS Guarantees
Event details
| Date | 17.04.2012 |
| Hour | 13:30 › 14:30 |
| Speaker | Christos Kozyrakis, Stanford University |
| Location | |
| Category | Conferences - Seminars |
Abstract :
As industry is heading towards chips with hundreds of cores, we need memory hierarchies that can support efficiently large processor counts. In fact, memory hierarchy is the most critical aspect of future multi-core architectures because the latency and energy overheads of remote memory accesses (on-chip or off-chip) dwarf the overheads of computational operations.
This talk will summarize three recent results towards scalable memory hierarchies. First, we will introduce Zcache, a technique that increases the number of replacement candidates in order to turn a low associativity cache into a high associativity cache without additional area or energy costs. Second, we will discuss Vantage, a scheme that allows us to divide a shared cache into hundreds of fine-grain partitions, while maintaining high associativity within each partition and providing strict size guarantees. Finally, we will present the SCD organization for coherence directories that scales to thousands of cores with constant latency and area/energy overheads that grow logarithmically to the number of cores.
More importantly, we can prove analytically and verify experimentally that the behavior of these techniques is independent of workload patterns. Hence, we can go beyond the conventional design approach of "make the common case fast" and build memory hierarchies
with strong quality of service guarantees across all usage (scalable) without significant over-provisioning of resources (energy efficient).
Bio :
Christos Kozyrakis is an Associate Professor of Electrical Engineering & Computer Science at Stanford University. He works on architectures, runtime environments, and programming models for parallel computing systems. At Berkeley, he developed the IRAM architecture, a novel media-processor system that combined vector processing with embedded DRAM technology. At Stanford, he led the Transactional Coherence and Consistency (TCC) project at Stanford that developed hardware and software mechanisms for programming with transactional memory. He also led the Raksha project, that developed practical hardware support and security policies to deter high-level and low-level security attacks against deployed software. Dr. Kozyrakis is currently working on hardware and software techniques for next-generation data centers. He is also a member of the Pervasive Parallelism Lab at Stanford, a multi-faculty effort to make parallel computing practical for the masses.
Christos received a BS degree from the University of Crete (Greece) and a PhD degree from the University of California at Berkeley (USA), both in Computer Science. He is the Willard R. and Inez Kerr Bell faculty scholar at Stanford and a senior member of the ACM and the IEEE. Christos has received the NSF Career Award, an IBM Faculty Award, the Okawa Fundantion Research Grant, and a Noyce Family Faculty Scholarship.
As industry is heading towards chips with hundreds of cores, we need memory hierarchies that can support efficiently large processor counts. In fact, memory hierarchy is the most critical aspect of future multi-core architectures because the latency and energy overheads of remote memory accesses (on-chip or off-chip) dwarf the overheads of computational operations.
This talk will summarize three recent results towards scalable memory hierarchies. First, we will introduce Zcache, a technique that increases the number of replacement candidates in order to turn a low associativity cache into a high associativity cache without additional area or energy costs. Second, we will discuss Vantage, a scheme that allows us to divide a shared cache into hundreds of fine-grain partitions, while maintaining high associativity within each partition and providing strict size guarantees. Finally, we will present the SCD organization for coherence directories that scales to thousands of cores with constant latency and area/energy overheads that grow logarithmically to the number of cores.
More importantly, we can prove analytically and verify experimentally that the behavior of these techniques is independent of workload patterns. Hence, we can go beyond the conventional design approach of "make the common case fast" and build memory hierarchies
with strong quality of service guarantees across all usage (scalable) without significant over-provisioning of resources (energy efficient).
Bio :
Christos Kozyrakis is an Associate Professor of Electrical Engineering & Computer Science at Stanford University. He works on architectures, runtime environments, and programming models for parallel computing systems. At Berkeley, he developed the IRAM architecture, a novel media-processor system that combined vector processing with embedded DRAM technology. At Stanford, he led the Transactional Coherence and Consistency (TCC) project at Stanford that developed hardware and software mechanisms for programming with transactional memory. He also led the Raksha project, that developed practical hardware support and security policies to deter high-level and low-level security attacks against deployed software. Dr. Kozyrakis is currently working on hardware and software techniques for next-generation data centers. He is also a member of the Pervasive Parallelism Lab at Stanford, a multi-faculty effort to make parallel computing practical for the masses.
Christos received a BS degree from the University of Crete (Greece) and a PhD degree from the University of California at Berkeley (USA), both in Computer Science. He is the Willard R. and Inez Kerr Bell faculty scholar at Stanford and a senior member of the ACM and the IEEE. Christos has received the NSF Career Award, an IBM Faculty Award, the Okawa Fundantion Research Grant, and a Noyce Family Faculty Scholarship.
Practical information
- Informed public
- Free
Contact
- Simone Muller