Towards Scalable and Holistic FPGA Routing
Event details
| Date | 04.06.2025 |
| Hour | 14:00 › 16:00 |
| Speaker | Alexandros Poupakis |
| Location | |
| Category | Conferences - Seminars |
EDIC candidacy exam
Exam president: Prof. Giovanni De Micheli
Thesis advisor: Prof. Babak Falsafi
Thesis co-advisor: Prof. Mirjana Stojilovic
Co-examiner: Prof. Michael Kapralov
Abstract
As FPGAs continue to scale in size and complexity,
traditional routing algorithms like PathFinder struggle with scalability
and solution quality due to inherent sequential decisionmaking
and dependence on net and sink order. This report
outlines the key pathologies of PathFinder, including inconsistent
results and convergence failures, and explores recent research
addressing these limitations. Inspired by global optimization
techniques used in VLSI routing, we propose a novel two-stage
FPGA routing framework: (1) independent, parallel generation
of multiple candidate route trees per net, followed by (2) global
selection of one tree per net via integer linear programming or
simulated annealing. This approach aims to improve scalability
and quality of results by decoupling local route tree construction
from global decision-making.
Selected papers
Timing-driven pathfinder pathology and remediation: quantifying and reducing delay noise in VPR-pathfinder
Fast integer linear programming based models for VLSI global routing
Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox
Exam president: Prof. Giovanni De Micheli
Thesis advisor: Prof. Babak Falsafi
Thesis co-advisor: Prof. Mirjana Stojilovic
Co-examiner: Prof. Michael Kapralov
Abstract
As FPGAs continue to scale in size and complexity,
traditional routing algorithms like PathFinder struggle with scalability
and solution quality due to inherent sequential decisionmaking
and dependence on net and sink order. This report
outlines the key pathologies of PathFinder, including inconsistent
results and convergence failures, and explores recent research
addressing these limitations. Inspired by global optimization
techniques used in VLSI routing, we propose a novel two-stage
FPGA routing framework: (1) independent, parallel generation
of multiple candidate route trees per net, followed by (2) global
selection of one tree per net via integer linear programming or
simulated annealing. This approach aims to improve scalability
and quality of results by decoupling local route tree construction
from global decision-making.
Selected papers
Timing-driven pathfinder pathology and remediation: quantifying and reducing delay noise in VPR-pathfinder
Fast integer linear programming based models for VLSI global routing
Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox
Practical information
- General public
- Free
Contact
- edic@epfl.ch