Versal: The Xilinx Adaptive Compute Acceleration Platform (ACAP) with AI engines

In this presentation we will present the new Adaptive Compute Acceleration Platform. We will show the overall system architecture of the family of devices including the Arm cores (scalar engines), the programmable logic (Adaptable Engines) and the new vector processor cores (AI engines). We will focus on the new AI engines in more detail and show the architecture, the integration in the total device, the programming environment and some applications, including Machine Learning and 5G wireless applications. The latest Silicon device contains 400 of these novel vector processor cores. We will present the direction of new research including the mapping of algorithms and machine learning applications to these multi-core systems.

Kees Vissers graduated from Delft University in the Netherlands. He worked at Philips Research in Eindhoven, the Netherlands, for many years. The work included Digital Video system design, HW –SW co-design, VLIW processor design and dedicated video processors. He was a visiting industrial fellow at Carnegie Mellon University and at UC Berkeley. He is heading a team of researchers at Xilinx. The research topics include next generation programming environments for processors and FPGA fabric, high-performance video systems, machine learning applications and architectures, wireless applications and datacenter applications. He has been instrumental in the High-Level Synthesis technology and one of the technical leads in the novel array of AI engines.

Stephen Neuendorffer graduated from UC Berkeley. He has worked at Xilinx for 14 years on various aspects of system design for FPGAs, including 5 years as product architect of Vivado HLS.  He is currently working in the Xilinx Research Labs with a focus on machine learning and next-generation devices.