2.5D and 3D IC --- The Status, The Challenges, and The Prospect

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Event details

Date and time 24.01.2014 11:0012:00  
Place and room
Speaker Hsien-Hsin Sean Lee, TSMC and Georgia Tech
Category Conferences - Seminars
As device scaling faces several fundamental changes due to physical limitations, tight integration in the vertical dimension emerges to be the frontrunner technology to continue Gordon Moore’s prophecy. A broad definition of vertical integration includes novel wafer-level packaging schemes, stacking multiple silicon dice on a passive silicon-interposer (2.5D), true 3D die-stacked IC, and monolithic 3D fabrication. These highly anticipated solutions not only pack more transistors on a given footprint to reduce the form factor, they also offer advantages such as immense memory bandwidth, low power consumption, fast interconnect, flexibility in integration, etc. In this talk, I will review and present my view, from industry’s perspective, on the latest art in 2.5D and 3D integration, their major challenges for market acceptance and productization, and the (near-)future outlook.

Practical information

  • Informed public
  • Free

Organizer

  • Babak Falsafi

Contact

  • Stéphanie Baillargues

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