2.5D and 3D IC --- The Status, The Challenges, and The Prospect
As device scaling faces several fundamental changes due to physical limitations, tight integration in the vertical dimension emerges to be the frontrunner technology to continue Gordon Moore’s prophecy. A broad definition of vertical integration includes novel wafer-level packaging schemes, stacking multiple silicon dice on a passive silicon-interposer (2.5D), true 3D die-stacked IC, and monolithic 3D fabrication. These highly anticipated solutions not only pack more transistors on a given footprint to reduce the form factor, they also offer advantages such as immense memory bandwidth, low power consumption, fast interconnect, flexibility in integration, etc. In this talk, I will review and present my view, from industry’s perspective, on the latest art in 2.5D and 3D integration, their major challenges for market acceptance and productization, and the (near-)future outlook.