Design Optimizations for On-Chip Networks

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Event details

Date and time 20.10.2009 15:15  
Place and room
Speaker Prof. Vijaykrishnan Narayanan
Category Conferences - Seminars
Abstract: Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for multicores/CMPs. In this talk, I will present an overview of several design optimizations aimed at improving the performance and power efficiency of on-chip routers. First, I will show the benefits of designing routers using 3D stacked technology. Second, I will show the use of hybrid topologies in enhancing the power and performance efficiencies in a NoC. Finally, I introduce an approach that tunes the frequency of a router in response to network load to manage both performance and power. Short CV: Vijaykrishnan Narayanan is a Professor at the Computer Science and Engineering department at The Pennsylvania State University with research interests in the areas of power-aware and reliable systems, embedded systems, reconfigurable architectures, nano-architectures and computer architecture. To learn more: Please visit http://www.cse.psu.edu/~vijay Vijaykrishnan Narayanan's homepage

Practical information

  • General public
  • Free

Contact

  • Michael Ferdman

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