EE-SRI: Nanolithography and CAD Challenges beyond-14nm
Event details
| Date | 22.06.2012 |
| Hour | 16:15 › 17:15 |
| Speaker | David Pan, University of Texas at Austin |
| Location |
Room MXF1
|
| Category | Conferences - Seminars |
As technology scales to 22nm, 14nm, 11nm and possibly beyond (e.g., EE Times article on 10/26/2011 TSMC's R&D chief sees 10 years of scaling), new nanolithography process technologies (including double/multiple patterning, EUV, E-beam lithography) have to be developed to keep pace of the scaling. These, coupled with process variations, leakage, and reliability issues will add more complexity and cost into the already-challenging design closure. In this talk, I will present some key challenges/issues and recent research results on design for manufacturing (DFM) with these nanolithography technologies, including layout decomposition with multiple patterning, E-beam lithography throughput improvement, litho-hotspot detection and litho-friendly physical designs.
Practical information
- Informed public
- Free
- This event is internal
Organizer
- EE Institute
Contact
- Philippe Gay-Balmaz, Suzanne Buffat