EPFL Workshop on Logic Synthesis and Verification

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Event details

Date 10.12.2015 11.12.2015
Hour 09:0017:00
Location
Category Conferences - Seminars
Nowadays, EDA tools face challenges tougher than ever. On the one hand, design sizes and goals in modern CMOS technology approach the frontier of what is possibly achievable. On the other hand, post-CMOS technologies bring new computational paradigms for which standard EDA tools are not suitable.
New research in fundamental EDA tasks, such as synthesis and verification, is key to handle this situation.

The EPFL Workshop on Logic Synthesis and Verification is a discussion forum on recent advancements and future evolution of synthesis and verification techniques in EDA. It will take place at EPFL, Lausanne, Switzerland on December 10-11, 2015. Top experts in the field will take part in the workshop to give presentations on cutting edge themes and to participate in panel discussions.

The EPFL Workshop on Logic Synthesis and Verification is funded by nano-tera.ch to promote international scientific exchanges.

Registeration is required to attend and is free of charge. Please register on-line by clicking here.

Practical information

  • General public
  • Registration required

Organizer

  • Prof. Giovanni De Micheli

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