From Microelectronics to Microsystems - the beauty of defects
Event details
| Date | 24.01.2017 |
| Hour | 11:00 |
| Speaker |
Prof. Jean-Pierre Raskin, UCL Bio: Prof. Jean-Pierre Raskin received the Industrial Engineer degree from the Institut Supérieur Industriel d’Arlon, Belgium, in 1993, and the M.S. and Ph.D. degrees in Applied Sciences from the Université catholique de Louvain (UCL), Louvain-la-Neuve, Belgium, in 1994 and 1997, respectively. In 1998, he joined the EECS Department of The University of Michigan, Ann Arbor, USA. He has been involved in the development and characterization of micromachining fabrication techniques for microwave and millimeter-wave circuits and microelectromechanical transducers/amplifiers working in harsh environments. In 2000, he joined the Microwave Laboratory of UCL, Louvain-la-Neuve, Belgium, as Associate Professor, and he has been a Full Professor since 2007. From September 2009 to September 2010, he was visiting professor at Newcastle University, Newcastle Upon Tyne, UK. Since 2014 he has been the head of the Electrical Engineering Department of UCL. His research interests are the modeling, wideband characterization and fabrication of advanced SOI MOSFETs as well as micro and nanofabrication of MEMS / NEMS sensors and actuators, including the extraction of intrinsic material properties at nanometer scale. He was the recipient of the Médaille BLONDEL 2015, famous French reward that honors each year a researcher for outstanding advances in science which have demonstrated a major impact in the electrical and electronics industry. He received the SOI Consortium Award in 2016 in recognition in his vision and pioneering work for RF SOI. |
| Location | |
| Category | Conferences - Seminars |
CIME Electron Microscopy Seminar Series
Limitations of nanotechnology might be source of inspiration. Two scientific results highlighting the great and surprising interest of fabrication processing defects such as interface traps and residual stress in thin films to solve critical issues in RF CMOS technology and materials characterization at nanometer scale, respectively, will be presented. Indeed, it has been demonstrated that the introduction of defects at Si-SiO2interface drastically improves the RF performance of Si-based substrate, while the microelectronics community tries to fabricate high-quality interfaces. And the great opportunity of internal stress in thin films to mechanically deform nanoscale materials on-chip is shown whereas the MEMS community tries to get rid of the internal stress in deposited thin films.
Today, thanks to trap-rich Silicon-on-Insulator (SOI) substrate, SOI-RF has displaced III-V on switch market thanks too much lower cost and better performance and opening the path for on-chip integration of full front end module.
This concept is today engineered in the industry, we can cite IBM which introduces defects underneath the buried oxide of SOI substrate by high energy ions implantation, and Soitec developed the eSI™ RF-SOI substrate which has been on the market since 2010. Almost all new Smart Phones have RF-SOI inside. It is really a success story starting from a fundamental breakthrough developed in the academic environment and transferred to the industry for serving great innovative products in the field of wireless communications which is one of the major technologies of the 21st century. In the field of material characterisation at nanometer scale, the on-chip traction test concept is now used by many research labs and centers around the world to investigate mechanical and coupled effects in a broad range of materials including the metallic glass, semiconductors and dielectrics.
Limitations of nanotechnology might be source of inspiration. Two scientific results highlighting the great and surprising interest of fabrication processing defects such as interface traps and residual stress in thin films to solve critical issues in RF CMOS technology and materials characterization at nanometer scale, respectively, will be presented. Indeed, it has been demonstrated that the introduction of defects at Si-SiO2interface drastically improves the RF performance of Si-based substrate, while the microelectronics community tries to fabricate high-quality interfaces. And the great opportunity of internal stress in thin films to mechanically deform nanoscale materials on-chip is shown whereas the MEMS community tries to get rid of the internal stress in deposited thin films.
Today, thanks to trap-rich Silicon-on-Insulator (SOI) substrate, SOI-RF has displaced III-V on switch market thanks too much lower cost and better performance and opening the path for on-chip integration of full front end module.
This concept is today engineered in the industry, we can cite IBM which introduces defects underneath the buried oxide of SOI substrate by high energy ions implantation, and Soitec developed the eSI™ RF-SOI substrate which has been on the market since 2010. Almost all new Smart Phones have RF-SOI inside. It is really a success story starting from a fundamental breakthrough developed in the academic environment and transferred to the industry for serving great innovative products in the field of wireless communications which is one of the major technologies of the 21st century. In the field of material characterisation at nanometer scale, the on-chip traction test concept is now used by many research labs and centers around the world to investigate mechanical and coupled effects in a broad range of materials including the metallic glass, semiconductors and dielectrics.
Practical information
- General public
- Free
Organizer
- Dr. Emad Oveisi, Interdisciplinary Centre for Electron Microscopy (CIME)
Contact
- Dr. Emad Oveisi, Interdisciplinary Centre for Electron Microscopy (CIME)