Generating Hardware Accelerators from High-Level Programming Languages
Event details
| Date | 01.07.2016 |
| Hour | 13:30 › 15:30 |
| Speaker | Lana Josipovic |
| Location | |
| Category | Conferences - Seminars |
EDIC Candidacy Exam
Exam President: Prof. Giovanni De Micheli
Thesis Director: Prof. Paolo Ienne
Co-examiner: Prof. Christos Kozyrakis
Background papers
Resource-Aware Throughput Optimization for High-Level
Synthesis
Automatic Support for Multi-Module Parallelism
from Computational Patterns
RTL Synthesis: From Logic Synthesis to Automatic
Pipelining
Abstract
Despite the numerous advantages of Field Programmable Gate Arrays (FPGAs), their usage is still restricted to a narrow segment of developers: those with hardware design experience. At the same time, high-level synthesis (HLS) is becoming increasingly popular as a way to broaden the developer base. However, HLS tools today suffer from numerous limitations and are not always able to deliver adequate design quality and performance. There is an immediate requirement to explore the generation of efficient, high-quality hardware accelerators from high-level programming languages. This would instantly enable the widespread acceptance of FPGAs, potentially leading to their adoption in many new market segments.
Exam President: Prof. Giovanni De Micheli
Thesis Director: Prof. Paolo Ienne
Co-examiner: Prof. Christos Kozyrakis
Background papers
Resource-Aware Throughput Optimization for High-Level
Synthesis
Automatic Support for Multi-Module Parallelism
from Computational Patterns
RTL Synthesis: From Logic Synthesis to Automatic
Pipelining
Abstract
Despite the numerous advantages of Field Programmable Gate Arrays (FPGAs), their usage is still restricted to a narrow segment of developers: those with hardware design experience. At the same time, high-level synthesis (HLS) is becoming increasingly popular as a way to broaden the developer base. However, HLS tools today suffer from numerous limitations and are not always able to deliver adequate design quality and performance. There is an immediate requirement to explore the generation of efficient, high-quality hardware accelerators from high-level programming languages. This would instantly enable the widespread acceptance of FPGAs, potentially leading to their adoption in many new market segments.
Practical information
- General public
- Free
Contact
- Cecilia Chapuis EDIC