IC Talk: Programmable Hardware (FPGAs) for Efficient Deep Learning Inference and Reinforcement Learning for Efficient FPGA CAD

Abstract: The first part of this talk discusses what FPGAs can do for deep learning. FPGAs are computer chips in which both the logic functions and the  connectivity between them can be reprogrammed, enabling custom processing pipelines where the numeric precision, memory layout and more can adapt to best match a deep learning (DL) algorithm and where the programmable I/O can enable unique embedded systems. We discuss the strengths and weaknesses of FPGAs in the DL domain, styles of DL accelerators that can be programmed into FPGAs to yield power-efficient and low-latency DL  acceleration, and some future research areas to enhance efficiency further.

The second part of this talk focuses on what reinforcement learning can do for FPGAs. The low-level programmability of FPGAs necessitates a complex computer-aided design (CAD) flow to translate a high-level specification by a hardware engineer into the millions of programming bits that configure the chip.  The most time-consuming part of this CAD flow is typically placement, which chooses where each one of hundreds of thousands or millions of hardware primitives should be located within the FPGA. We will discuss how reinforcement learning can be combined with the simulated annealing meta-heuristic to find quality-enhancing perturbations of a placement, reducing the CPU time needed to obtain an acceptable solution by over 2X.


Bio:  Vaughn Betz is a Professor at the University of Toronto in the Department of Electrical and Computer Engineering, and a Faculty Affiliate of the Vector  Institute for Artificial Intelligence. He is the original developer of the widely used VPR FPGA placement, routing and architecture evaluation CAD flow, and a  lead developer in the VTR project that has built upon VPR. He co-founded Right Track CAD to develop new FPGA CAD tools and architectures, and joined  Altera upon Right Track CAD’s acquisition. Dr. Betz spent 11 years at Altera (now part of Intel), ultimately as Senior Director of software engineering, and is  one of the architects of the Quartus CAD system and the first five generations of the Stratix and Cyclone FPGA families. He holds 102 US patents and has  published over 150 technical articles in the FPGA area, fifteen of which have won best or most significant paper awards. Dr. Betz is a Fellow of the IEEE, the  National Academy of Inventors and the Engineering Institute of Canada.