IEM Distinguished Lecturers Seminar: Making Every Chip Hardware-Secure and Physically-Patchable – From Physical Design to On-Chip Machine Learning
Event details
| Date | 17.01.2025 |
| Hour | 10:00 › 11:00 |
| Speaker |
Prof. Massimo Alioto, ECE - National University of Singapore |
| Location | Online |
| Category | Conferences - Seminars |
| Event Language | English |
***Coffee and cookies will be served at 9h45 in the hall of BM 5202***
Abstract
In next-generation secure silicon chips, divide-and-conquer design methodologies facilitate building block design but conflict with basic hardware security requirements. Also, they preclude opportunities for efficient system integration and inexpensive embedment of security features. At the same time, the insertion of security primitives as standalone blocks is inherently additive in terms of area, power, design effort and integration effort, limiting their embeddability in low-cost devices (i.e., the vast majority of the upcoming trillion chips for the Internet of Things). As further limitation of conventional approaches to security enforcement in silicon chips (e.g., against side-channel attacks), the discovery of hardware vulnerabilities cannot be followed by later hardware fixes as we are used to do with software systems.
In this keynote, the road towards ubiquitous hardware security is pursued from a primitive design perspective, designing PUFs and TRNGs that are inherently immersed in existing memory arrays and logic fabrics, and breaking the boundaries of traditional system partitioning. The new concept of hardware patching is also discussed, where circuit flexibility is introduced to make silicon chips able to evolve over time and counteract newly discovered vulnerabilities through learning-based physical protection mechanisms.
Bio
Massimo Alioto is a Professor at the ECE Department of the National University of Singapore, where he leads the Green IC group, the Integrated Circuits and Embedded Systems area, and the FD-fAbrICS center on intelligent&connected systems. Previously, he held positions at the University of Siena, Intel Labs – CRL (2013), University of Michigan - Ann Arbor (2011-2012), University of California – Berkeley (2009-2011), EPFL - Lausanne.
He is (co)author of 400 publications on journals and conference proceedings, and four books with Springer (with two more coming this quarter). His primary research interests include ultra-low power and self-powered systems, green computing, circuits for machine intelligence, hardware security, and emerging technologies.
He was the Editor in Chief of the IEEE Transactions on VLSI Systems and Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems. He is/was the Chair of the Distinguished Lecturer Program for the IEEE CAS Society, and Distinguished Lecturer for the SSC and CAS Society. Previously, Prof. Alioto was the Chair of the “VLSI Systems and Applications” Technical Committee of the IEEE Circuits and Systems Society (2010-2012). He served as Guest Editor of numerous journal special issues (JSSC, TCAS-I, JETCAS…), Technical Program Chair of several IEEE conferences (ISCAS, SOCC, PRIME, ICECS), and TPC member (ISSCC, ASSCC). His research group contribution has been recognized through various best paper awards (e.g., ISSCC, ICECS), and in the ten technological highlights of the TSMC 2020 annual report, among the others. Prof. Alioto is an IEEE Fellow.
Abstract
In next-generation secure silicon chips, divide-and-conquer design methodologies facilitate building block design but conflict with basic hardware security requirements. Also, they preclude opportunities for efficient system integration and inexpensive embedment of security features. At the same time, the insertion of security primitives as standalone blocks is inherently additive in terms of area, power, design effort and integration effort, limiting their embeddability in low-cost devices (i.e., the vast majority of the upcoming trillion chips for the Internet of Things). As further limitation of conventional approaches to security enforcement in silicon chips (e.g., against side-channel attacks), the discovery of hardware vulnerabilities cannot be followed by later hardware fixes as we are used to do with software systems.
In this keynote, the road towards ubiquitous hardware security is pursued from a primitive design perspective, designing PUFs and TRNGs that are inherently immersed in existing memory arrays and logic fabrics, and breaking the boundaries of traditional system partitioning. The new concept of hardware patching is also discussed, where circuit flexibility is introduced to make silicon chips able to evolve over time and counteract newly discovered vulnerabilities through learning-based physical protection mechanisms.
Bio
Massimo Alioto is a Professor at the ECE Department of the National University of Singapore, where he leads the Green IC group, the Integrated Circuits and Embedded Systems area, and the FD-fAbrICS center on intelligent&connected systems. Previously, he held positions at the University of Siena, Intel Labs – CRL (2013), University of Michigan - Ann Arbor (2011-2012), University of California – Berkeley (2009-2011), EPFL - Lausanne.
He is (co)author of 400 publications on journals and conference proceedings, and four books with Springer (with two more coming this quarter). His primary research interests include ultra-low power and self-powered systems, green computing, circuits for machine intelligence, hardware security, and emerging technologies.
He was the Editor in Chief of the IEEE Transactions on VLSI Systems and Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems. He is/was the Chair of the Distinguished Lecturer Program for the IEEE CAS Society, and Distinguished Lecturer for the SSC and CAS Society. Previously, Prof. Alioto was the Chair of the “VLSI Systems and Applications” Technical Committee of the IEEE Circuits and Systems Society (2010-2012). He served as Guest Editor of numerous journal special issues (JSSC, TCAS-I, JETCAS…), Technical Program Chair of several IEEE conferences (ISCAS, SOCC, PRIME, ICECS), and TPC member (ISSCC, ASSCC). His research group contribution has been recognized through various best paper awards (e.g., ISSCC, ICECS), and in the ten technological highlights of the TSMC 2020 annual report, among the others. Prof. Alioto is an IEEE Fellow.
Practical information
- General public
- Free