Logic Synthesis and Optimization for Emerging Technologies
Event details
| Date | 28.06.2021 |
| Hour | 14:00 › 16:00 |
| Speaker | Dewmini Marakkalage |
| Category | Conferences - Seminars |
EDIC candidacy exam
exam president: Prof. Paolo Ienne
thesis advisor: Prof. Giovanni De Micheli
co-examiner: Prof. Andreas Burg
expert: Dr. Heinz Riener
Abstract
The existing digital logic synthesis tools are tailored to the needs of complementary metal-oxide-semiconductor (CMOS) technology which has been the dominant electronics technology for decades.
However, enabled by recent technological advancements and fueled by the drive for high-speed energy-efficient computation, alternate forms of electronic technologies such as superconducting electronics (SCE) are gaining pace.
The existing CMOS-specific synthesis tools, however, are unable to fully exploit the benefits of such technologies as such tools are not optimized for these technologies and are not equipped to deal with the additional constraints such as clocked logic gates they impose.
In this research proposal, we first look at one recently proposed synthesis flow for a particular superconducting technology called adiabatic quantum-flux-parametron (AQFP).
We then look at a versatile synthesis approach called SAT-based exact synthesis which seems promising as a tool for synthesizing optimal circuit structures under various constraints for functions of a few variables and study how that approach could help the synthesis algorithms for larger logic networks in emerging technologies.
In this regard, we also study a depth-optimal polynomial-time rewriting algorithm for FPGA technology mapping that has wider implications and discuss its benefits and drawbacks.
We finally propose a high-level overview of our research plan which broadly aims at developing new logic synthesis algorithms targeting post-CMOS technologies.
Background papers
1. "A semi-custom design methodology and environment for implementing superconductor adiabatic quantum-flux-parametron microprocessors",
https://iopscience.iop.org/article/10.1088/1361-6668/ab7ec3/meta
2. "SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism" https://ieeexplore.ieee.org/abstract/document/8634910?casa_token=J7M9Rn-prBYAAAAA:wD0RbwerD2BzV9T8cYW4-o3zguu8FvC4Lv1r8u_qXT2Mys05_jmu87TF4Trj9zAOkeLQkbnSFw
3. "FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs"
https://ieeexplore.ieee.org/abstract/document/273754
exam president: Prof. Paolo Ienne
thesis advisor: Prof. Giovanni De Micheli
co-examiner: Prof. Andreas Burg
expert: Dr. Heinz Riener
Abstract
The existing digital logic synthesis tools are tailored to the needs of complementary metal-oxide-semiconductor (CMOS) technology which has been the dominant electronics technology for decades.
However, enabled by recent technological advancements and fueled by the drive for high-speed energy-efficient computation, alternate forms of electronic technologies such as superconducting electronics (SCE) are gaining pace.
The existing CMOS-specific synthesis tools, however, are unable to fully exploit the benefits of such technologies as such tools are not optimized for these technologies and are not equipped to deal with the additional constraints such as clocked logic gates they impose.
In this research proposal, we first look at one recently proposed synthesis flow for a particular superconducting technology called adiabatic quantum-flux-parametron (AQFP).
We then look at a versatile synthesis approach called SAT-based exact synthesis which seems promising as a tool for synthesizing optimal circuit structures under various constraints for functions of a few variables and study how that approach could help the synthesis algorithms for larger logic networks in emerging technologies.
In this regard, we also study a depth-optimal polynomial-time rewriting algorithm for FPGA technology mapping that has wider implications and discuss its benefits and drawbacks.
We finally propose a high-level overview of our research plan which broadly aims at developing new logic synthesis algorithms targeting post-CMOS technologies.
Background papers
1. "A semi-custom design methodology and environment for implementing superconductor adiabatic quantum-flux-parametron microprocessors",
https://iopscience.iop.org/article/10.1088/1361-6668/ab7ec3/meta
2. "SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism" https://ieeexplore.ieee.org/abstract/document/8634910?casa_token=J7M9Rn-prBYAAAAA:wD0RbwerD2BzV9T8cYW4-o3zguu8FvC4Lv1r8u_qXT2Mys05_jmu87TF4Trj9zAOkeLQkbnSFw
3. "FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs"
https://ieeexplore.ieee.org/abstract/document/273754
Practical information
- General public
- Free
Organizer
- EDIC