Machine Learning for FPGA Computer-Aided Design
Event details
| Date | 16.06.2022 |
| Hour | 09:30 › 11:30 |
| Speaker | Shashwat Shrivastava |
| Location | |
| Category | Conferences - Seminars |
EDIC candidacy exam
Exam president: Prof. Giovani De Micheli
Thesis advisor: Prof. Babak Falsafi
Thesis co-advisior: Dr. Mirjana Stojilovic
Co-examiner: Prof. Patrick Thiran
Abstract
FPGAs have proven to be an efficient platform for applications in the domain of video and image processing, machine learning, genomics, wireless communication, scientific computations, and medical. The diversity of domains targeted by FPGAs accounts from the fact that they offer reprogrammability, low-power consumption, fine-grained parallelism, and short design time as compared to ASICs. However, the term 'short design time' is often misleading. With technology scaling, the design time of FPGA designs varies from hours to days. Moreover, the same design flow is repeated multiple times to achieve satisfactory hardware implementation.
FPGA CAD flow (or compilation flow) comprises four main stages, out of which, placement and routing take up the maximum amount of time. The traditional approaches produce satisfactory sub-optimal results (given NP-completeness of problems), however, have long runtimes. Researchers have tried to integrate some Machine Learning techniques in the FPGA CAD flow to speed-up placement. However, little has been done to accelerate the routing process while maintaining the high Quality of Results (QoR). In my thesis, I would like to develop an ML-driven routing algorithm that achieves high QoR at high speed.
Background papers
Paper 1. PathFinder: A Negotiation-based Performance-driven Router for FPGAs (Listed in 25 most influential papers for FPGAs)
Paper 2. Machine-Learning Based Congestion Estimation for Modern FPGAs (Best paper award FPL'2018)
Paper 3. GPlace3.0: Routability-Driven Analytic Placer for UltraScale FPGA Architectures
Exam president: Prof. Giovani De Micheli
Thesis advisor: Prof. Babak Falsafi
Thesis co-advisior: Dr. Mirjana Stojilovic
Co-examiner: Prof. Patrick Thiran
Abstract
FPGAs have proven to be an efficient platform for applications in the domain of video and image processing, machine learning, genomics, wireless communication, scientific computations, and medical. The diversity of domains targeted by FPGAs accounts from the fact that they offer reprogrammability, low-power consumption, fine-grained parallelism, and short design time as compared to ASICs. However, the term 'short design time' is often misleading. With technology scaling, the design time of FPGA designs varies from hours to days. Moreover, the same design flow is repeated multiple times to achieve satisfactory hardware implementation.
FPGA CAD flow (or compilation flow) comprises four main stages, out of which, placement and routing take up the maximum amount of time. The traditional approaches produce satisfactory sub-optimal results (given NP-completeness of problems), however, have long runtimes. Researchers have tried to integrate some Machine Learning techniques in the FPGA CAD flow to speed-up placement. However, little has been done to accelerate the routing process while maintaining the high Quality of Results (QoR). In my thesis, I would like to develop an ML-driven routing algorithm that achieves high QoR at high speed.
Background papers
Paper 1. PathFinder: A Negotiation-based Performance-driven Router for FPGAs (Listed in 25 most influential papers for FPGAs)
Paper 2. Machine-Learning Based Congestion Estimation for Modern FPGAs (Best paper award FPL'2018)
Paper 3. GPlace3.0: Routability-Driven Analytic Placer for UltraScale FPGA Architectures
Practical information
- General public
- Free