Optimizing communication architecture for many-core systems
Event details
| Date | 17.09.2015 |
| Hour | 16:00 › 17:00 |
| Speaker | Jinho Lee, ECE, Seoul National University, Korea |
| Location | |
| Category | Conferences - Seminars |
Network-on-chip and processing-in-memory
As more and more components tend to be integrated on a system, the importance of optimizing interconnects has been continuously growing. In this talk, I will introduce some optimization techniques for the on-chip and off-chip interconnects.
The first part is about two routing algorithms for 3D stacked network-on-chips. The 3D stacking technology can provide many opportunities to designing computing systems. However, most solutions for vertical communication, such as TSVs and inductive coupling suffer from the high cost and thus their numbers are often severely limited. I will investigate the design options for building 3D NoCs in such environment, and propose routing algorithms for each option.
The second part targets the off-chip link between processor and the main memory. For years, the memory wall problem has been limiting the scaling of many-core systems. To mitigate this, the old “processing-in-memory” paradigm is being revived to reduce the bandwidth requirements. I will present an approach to placing lightweight logic inside DRAM to gain significant speedups for a set of big-data kernels.
As more and more components tend to be integrated on a system, the importance of optimizing interconnects has been continuously growing. In this talk, I will introduce some optimization techniques for the on-chip and off-chip interconnects.
The first part is about two routing algorithms for 3D stacked network-on-chips. The 3D stacking technology can provide many opportunities to designing computing systems. However, most solutions for vertical communication, such as TSVs and inductive coupling suffer from the high cost and thus their numbers are often severely limited. I will investigate the design options for building 3D NoCs in such environment, and propose routing algorithms for each option.
The second part targets the off-chip link between processor and the main memory. For years, the memory wall problem has been limiting the scaling of many-core systems. To mitigate this, the old “processing-in-memory” paradigm is being revived to reduce the bandwidth requirements. I will present an approach to placing lightweight logic inside DRAM to gain significant speedups for a set of big-data kernels.
Practical information
- Informed public
- Free
Organizer
- Babak Falsafi
Contact
- Stéphanie Baillargues