Processor Microarchitectural Optimizations for Performance Density

EDIC candidacy exam
Exam president: Prof. Thomas Bourgeat
Thesis advisor: Prof. Babak Falsafi
Co-examiner: Prof. David Ateinza

Abstract
As we reach the end of Moore's Law and Dennard Scaling, we cannot rely on transistor scaling to improve the performance and efficiency of processors. Instead, we need to rely on architectural and microarchitectural design techniques to improve the performance and efficiency of processors. In the server workloads, the performance density, i.e. performance per unit silicon area, is one of the most important metrics to achieve higher total performance with a given area for server processors. The research proposal focuses on architectural and microarchitectural design techniques such as cache coherence, Out-of-Order (OoO) execution, and Simultaneous Multithreading (SMT) to improve the performance density of server processors.

Background papers
1) Scale-Out Processors [ISCA12'] https://dl.acm.org/doi/10.1145/2366231.2337217 Pejman Lotfi-Kamran, Boris Grot, Michael Ferdman, Stavros Volos, Onur Kocberber, Javier Picorel, Almutaz Adileh, Djordje Jevdjic, Sachin Idgunji, Emre Ozer, and Babak Falsafi.
2) MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP [MICRO12'] https://ieeexplore.ieee.org/document/6493629 Khubaib, M. A. Suleman, M. Hashemi, C. Wilkerson and Y. N. Patt
3) Mirage cores: the illusion of many out-of-order cores using in-order hardware [MICRO17'] https://ieeexplore.ieee.org/document/8686674 S. Padmanabha, A. Lukefahr, R. Das and S. Mahlke