RISC-V: Instruction sets want to be free
|Date and time||22.05.2017 – 10:30 › 11:45|
|Place and room|
|Speaker||Krste Asanović, Professor in the EECS Department at the University of California, Berkeley|
|Category||Conferences - Seminars|
The most important interface in a computer system is the instruction set architecture (ISA) as it connects software to hardware. So, given the prevalence of open standards for almost all other important interfaces, why is the ISA still proprietary? We argue that a free ISA is a necessary precursor to future hardware innovation, and there's no good technical reason not to have free, open ISAs just as we have free, open networking standards and free, open operating systems.
The free and open RISC-V ISA began development at UC Berkeley in 2010, with the frozen base user ISA standard released in May 2014, and has since seen rapid uptake around the globe, including the first commercial shipments. This talk will cover the technical features of the RISC-V ISA design, which has the goals of scaling from the tiniest implementations for IoT up to the largest warehouse-scale computers, with support for extensive customization. We'll also describe three different industry-competitive open-source cores developed at UC Berkeley, all written in Chisel, a productive new open-source hardware
design language. Finally, we'll describe the uptake of RISC-V and the development of the RISC-V ecosystem, including the RISC-V Foundation.