Breaking out of Control-Flow Jail: Single Assignment Compiler, Single-Assignment Architecture
Event details
| Date | 16.07.2015 |
| Hour | 13:30 › 14:30 |
| Speaker |
Dr. Soner Onder Short Bio: Dr. Soner Onder is a professor at the Department of Computer Science, Michigan Technological University where he leads the Computer Architecture Research Lab. His research interests span Architecture, Simulation and Programming languages, with an emphasis on program representations and compiler/architecture collaboration. He is the designer and implementor of one of the earliest architecture description languages, ADL. Dr. Soner Onder received his BS in Chemical Engineering in 1983, his MS in Computer Engineering in 1988 from Middle East Technical University, Ankara and his PhD in Computer Science from the University of Pittsburgh in 1999. He started at Michigan Tech in 1999. His research has been supported by National Science Foundation and DARPA. Dr. Onder is a recipient of National Science Foundation's CAREER award in 2004. |
| Location | |
| Category | Conferences - Seminars |
During the past two decades, micro-architecture research has primarily concentrated on exploiting program properties. We
observed that memory references of programs exhibit significant amount of temporal and spatial locality. We exploit the
locality of references by using cache structures at the micro-architecture level. We realized that memory access
patterns are predictable. We exploit this predictability by prefetching data to combat memory access latency. We noticed
that branch instructions exhibit very predictable behavior and their behavior is correlated with other branches.
We use these properties to design better branch predictors. Following years of success in understanding and
exploiting these properties, we have reached a plateau where obtaining significant gains by utilizing program properties
is no longer feasible.
Today, both the computing industry and academia have concentrated their efforts on thread-level and data-parallel
architectures, citing the power constraints and the end of Dennard scaling. While the number of transistors per chip
continued to increase until the age of dark-silicon, these transistors have mostly been utilized to build larger on-chip
storage as new micro-architecture techniques failed to demonstrate a commensurate increase in performance for the added
complexity. Therefore, I argue that we have reached not only the end of Dennard scaling but also the limits of
the control flow paradigm.
In this talk, I will show that the middle layer of the series of abstractions which extend from problems to
micro-architecture, namely, the program representation, is key to unleashing the performance potential of large hardware
resources. I will present our work on a new program representation called Future Gated Single Assignment Form (FGSA)
which represents programs in a partial-order that permits massive exploitation of instruction-level parallelism.
Moreover, FGSA can play a dual role as the compiler's internal representation and the instruction set architecture of
hardware. As a result, it can be employed by compilers as a drop-in replacement for Static Single Assignment (SSA) form
and it can be executed directly by control flow, data flow, or demand-driven architectures because it directly supports
all three models. FGSA can be derived from functional, imperative, or demand-driven languages and thus also provides a
path towards a unification of programming languages.
I will conclude by discussing our efforts to explore and develop demand-driven computing as a viable alternative to
control-flow computing. I will give an overview of a LaZy micro-architecture which can execute traditional code and
discuss how massively parallel demand-driven architectures can be built based on the FGSA representation.
Refreshments will be available before the talk as of 1:15pm.
observed that memory references of programs exhibit significant amount of temporal and spatial locality. We exploit the
locality of references by using cache structures at the micro-architecture level. We realized that memory access
patterns are predictable. We exploit this predictability by prefetching data to combat memory access latency. We noticed
that branch instructions exhibit very predictable behavior and their behavior is correlated with other branches.
We use these properties to design better branch predictors. Following years of success in understanding and
exploiting these properties, we have reached a plateau where obtaining significant gains by utilizing program properties
is no longer feasible.
Today, both the computing industry and academia have concentrated their efforts on thread-level and data-parallel
architectures, citing the power constraints and the end of Dennard scaling. While the number of transistors per chip
continued to increase until the age of dark-silicon, these transistors have mostly been utilized to build larger on-chip
storage as new micro-architecture techniques failed to demonstrate a commensurate increase in performance for the added
complexity. Therefore, I argue that we have reached not only the end of Dennard scaling but also the limits of
the control flow paradigm.
In this talk, I will show that the middle layer of the series of abstractions which extend from problems to
micro-architecture, namely, the program representation, is key to unleashing the performance potential of large hardware
resources. I will present our work on a new program representation called Future Gated Single Assignment Form (FGSA)
which represents programs in a partial-order that permits massive exploitation of instruction-level parallelism.
Moreover, FGSA can play a dual role as the compiler's internal representation and the instruction set architecture of
hardware. As a result, it can be employed by compilers as a drop-in replacement for Static Single Assignment (SSA) form
and it can be executed directly by control flow, data flow, or demand-driven architectures because it directly supports
all three models. FGSA can be derived from functional, imperative, or demand-driven languages and thus also provides a
path towards a unification of programming languages.
I will conclude by discussing our efforts to explore and develop demand-driven computing as a viable alternative to
control-flow computing. I will give an overview of a LaZy micro-architecture which can execute traditional code and
discuss how massively parallel demand-driven architectures can be built based on the FGSA representation.
Refreshments will be available before the talk as of 1:15pm.
Practical information
- Informed public
- Free
Organizer
- EcoCloud / Babak Falsafi
Contact
- Valérie Locca / EcoCloud