EE Seminar: From Deep Scaling to Deep Intelligence
Event details
| Date | 26.07.2019 |
| Hour | 14:00 › 15:00 |
| Speaker | Dr. Rajiv V. Joshi is a research staff member and key technical lead at T. J.Watson research center, IBM. He received his B.Tech I.I.T (Bombay, India), M.S (M.I.T) and Dr. Eng. Sc. (Columbia University). His novel interconnects processes and structures for aluminum, tungsten and copper technologies which are widely used in IBM for various technologies from sub-0.5μm to 14nm. He has led successfully predictive failure analytic techniques for yield prediction and also the technology-driven SRAM at IBM Server Group. He has extensively worked on novel memory designs. He commercialized these techniques. He received 3 Outstanding Technical Achievement (OTAs), 3 highest Corporate Patent Portfolio awards for licensing contributions, holds 58 invention plateaus and has over 225 US patents and over 350 including international patents. He has authored and co-authored over 190 papers. He has given over 45 invited/keynote talks and given several Seminars. He is awarded prestigious IEEE Daniel Noble award for 2018. He received the Best Editor Award from IEEE TVLSI journal. He is recipient of 2015 BMM award. He is inducted into New Jersey Inventor Hall of Fame in Aug 2014 along with pioneer Nicola Tesla. He is a recipient of 2013 IEEE CAS Industrial Pioneer award and 2013 Mehboob Khan Award from Semiconductor Research Corporation. He is a member of IBM Academy of technology. He served as a Distinguished Lecturer for IEEE CAS and EDS society. He is Distinguished visiting professor at IIT, Roorkie. He is IEEE, ISQED andWorld Technology Network fellow and distinguished alumnus of IIT Bombay. He is in the Board of Governors for IEEE CAS. He serves as an Associate Editor of TVLSI. He served on committees of ISCAS 2017, ISLPED (Int. Symposium Low Power Electronic Design), IEEE VLSI design, IEEE CICC, IEEE Int. SOI conference, ISQED and Advanced Metallization Program committees. He served as a general chair for IEEE ISLPED. He is an industry liaison for universities as a part of the Semiconductor Research Corporation. Also, he is in the industry liaison committee for IEEE CAS society. |
| Location | |
| Category | Conferences - Seminars |
Abstract : Moore’s law driving the advancement in semiconductor industry over decades has been coming to a screeching halt and many researchers are convinced that it is almost dead. After revival and promise of artificial intelligence (AI) due to increased computational performance and memory bandwidth aided by Moore’s law there is overwhelming enthusiasm in researchers for increasing the pace of VLSI industry. AI uses many neural network techniques for computation which involves training and inference.
The advancement in AI requires energy efficient, low power hardware systems. This is more so for servers, main processors, Internet of Things (IoT) and System on chip (SOC) applications and newer applications in cognitive computing. In the light of AI this talk focuses on advanced technology issues, important circuit techniques for lowering power, improving performance and functionality in nanoscale VLSI design in the midst of variability. The same techniques can be used for AI specific accelerators.
Accelerator development for reduction in power and throughput improvement for both edge and data centric accelerators compared to GPUs used for Convolutional Neural (CNN) and Deep Neural (DNN) Networks are described. The talk covers memory (volatile and nonvolatile) solutions for CNN/DNN applications at extremely low Vmin. Finally, the talk summarizes challenges and future directions for circuit applications for edge and data-centric accelerators.
The advancement in AI requires energy efficient, low power hardware systems. This is more so for servers, main processors, Internet of Things (IoT) and System on chip (SOC) applications and newer applications in cognitive computing. In the light of AI this talk focuses on advanced technology issues, important circuit techniques for lowering power, improving performance and functionality in nanoscale VLSI design in the midst of variability. The same techniques can be used for AI specific accelerators.
Accelerator development for reduction in power and throughput improvement for both edge and data centric accelerators compared to GPUs used for Convolutional Neural (CNN) and Deep Neural (DNN) Networks are described. The talk covers memory (volatile and nonvolatile) solutions for CNN/DNN applications at extremely low Vmin. Finally, the talk summarizes challenges and future directions for circuit applications for edge and data-centric accelerators.
Practical information
- General public
- Free
Organizer
- Prof. Andreas Burg, and Prof. David Atienza, Institute of EE (IEL), Faculty of Engineering (STI)
Contact
- [email protected] / +41 21 69 31131, [email protected] / +41 21 69 36924