Floating Point System Level Designs
Event details
| Date | 16.06.2009 |
| Hour | 15:15 |
| Speaker | Mr Martin Langhammer, Altera Corporation |
| Location | |
| Category | Conferences - Seminars |
Current FPGA devices are optimized for fixed point applications; the DSP precision, logic to DSP ratios, and especially the routing density are all architected for fixed point datapath requirements. Although small floating point datapaths can readily be implemented, large systems with several hundred operators are impossible, or result in severe performance degradation. A simple analysis shows that the routing density needs to be doubled in order to support IEEE754 floating point arithmetic, but the increased device area would not be commercially feasible. In addition, many algebraic and transcendental functions have been traditionally implemented using CORDIC or other bit-iterative methods, which despite mapping well to FPGA logic structures, cause severe routing stress. Recently, some new methods of floating point datapath construction, such as fused floating point datapath synthesis, have been proposed, which result in large logic, routing, and latency reductions. Combined with newer function architectures, which offer linear cost and latency tradeoffs for traditionally non-linear complexity, the construction of dense floating point systems with a very flexible operator mix is now possible. Design examples will be shown, involving hundreds of floating point operators, with pushbutton timing closure to the same performance levels as fixed point designs. In particular, matrix operation implementations such as matrix multiplication and Cholesky decomposition will be described, along with the algorithmic changes required to optimally use the wide, but deeply pipelined, vector operations that result from these new methods.
Practical information
- General public
- Free