PARSA seminar: Tagless Directory Coherence and Phantom-BTB
While modern processors are capable of processing data at never before seen speeds, this capability must be matched with an equally capable memory system. It is for this reason that a large chunk of modern processor chips is devoted to the memory hierarchy. Our work has been looking at the design of these memory hierarchies. I will overview two recent results. The first, Phantom-BTB, freeloads on the existing memory hierarchy to store program metadata. This is information about program behavior that is used at runtime to anticipate performance or other degrading events and act accordingly to improve system behavior. Phantom-BTB uses the on-chip memory hierarchy to obtain the performance possible with otherwise impractical to build (too large and too slow) structures. The second work, revisits on-chip memory coherence, that is, how a processor can find where and who has copies of cached memory data. Coherence can greatly impact program performance in today's chip multiprocessors. Taking advantage of the opportunities that on-chip integration offers, tagless coherence reduces the cost of implementing coherence while maintaining competitive performance. BIO: Andreas Moshovos is an associate professor at the University of Toronto. He has taught computer architecture also at Northwestern University, the Hellenic Open University and the National University of Athens, Greece. He learned about computer architecture first at the University of Crete, Greece, and then at the University of Wisconsin- Madison where he worked on memory dependence prediction, a technique used in many modern processor designs, until 1998. Andreas is interested in designing computer systems that take advantage of program behavior to improve performance, power and other characteristics. He received the National Science Foundation CAREER award in 2000, a Semiconductor Research Corporation Inventor Recognition Award in 2003, and IBM Faculty Partnership Awards in 2008 and 2009.