See in the Dark Low-light / Low-noise CMOS Image Sensors
Event details
| Date | 14.11.2016 |
| Hour | 17:15 |
| Speaker | Prof. Christian Enz, EPFL |
| Location | |
| Category | Conferences - Seminars |
The continuous improvements of CMOS image sensors (CIS) in terms of quantum efficiency, speed, resolution, etc. enabled these low-cost devices to be used also in high-performance applications, progressively replacing charge coupled devices (CCDs). Photoelectron counting capability is the next step for CIS for ultimate low light performance and new imaging paradigms. With the recent improvements of the CIS sensitivity, the sub-electron read noise limit has been reached. But this low noise level remains a bottleneck and further reduction towards deep sub-electron noise is required.
In this talk we will present some recent results achieved in our lab in the field of low-noise CIS. We will start with a review of fundamental noise mechanisms found in 4 transistors (4T) pixels based on pinned photodiodes (PPD) and the associated readout chain circuits showing that the noise coming from the readout electronics is dominant. After a detailed noise analysis of the whole chain, different noise reduction techniques are identified. Among these techniques, it is proposed to replace the traditional in-pixel thick oxide amplifying transistor with a thin oxide device for achieving minimum 1/f noise. This technique was evaluated in a first test chip designed in a 180 nm CIS process and embedding optimized readout chains exploiting the new pixels together with state-of-the-art 4T pixels optimized at process level for low 1/f noise. A mean input-referred noise of 0.4 erms was measured demonstrating a factor two reduction compared to the state-of-the-art pixels. A full VGA imager including a 4T pixel of 6.5 µm pitch with a properly sized and biased thin oxide PMOS source follower was then integrated in the same standard CIS process. The imager features an input-referred noise histogram from 0.25 e-rms to a few erms peaking at 0.48 erms at room temperature. This sub-0.5 erms noise performance is obtained with a full well capacity of 6400 e and a frame rate that can go up to 80 fps. The VGA imager also features a fixed pattern noise as low as 0.77%, a lag of 0.1% and a dark current of 5.6 e/s.
The integrated chip used a simple correlated double sampling (CDS) noise reduction technique. We will show that further noise reduction can be achieved thanks to correlated multiple sampling (CMS) using very energy- and area-efficient passive switched-capacitor circuits. We will finish by looking at how CMOS technology scaling can help to further reduce the input-referred noise, potentially bringing it close to or even below the photoelectron counting limit.
Bio: Christian Enz, PhD, Swiss Federal Institute of Technology (EPFL), 1989. He is currently full Professor at EPFL and Director of the Institute of Microengineering (IMT) and head of the IC Lab. He is also the manager of the EPFL site at Microcity in Neuchâtel. Until April 2013 he was VP at the Swiss Center for Electronics and Microtechnology (CSEM) in Neuchâtel, Switzerland where he was heading the Integrated and Wireless Systems Division. Prior to joining the CSEM, he was Principal Senior Engineer at Conexant (formerly Rockwell Semiconductor Systems), Newport Beach, CA, where he was responsible for the modeling and characterization of MOS transistors for RF applications.
From 1992 to 1997, he was an Assistant Professor at EPFL, working in the field of low-power analog CMOS IC design and device modeling. In 1989 he was one of the founders of Smart Silicon Systems S.A. (S3), where he developed several low-noise and low-power ICs, mainly for high energy physics application at CERN. His technical interests and expertise are in the field of ultralow-power analog and RF IC design, wireless sensor networks and semiconductor device modeling. Together with E. Vittoz and F. Krummenacher he is the developer of the EKV MOS transistor model and the author of the book "Charge-Based MOS Transistor Modeling - The EKV Model for Low-Power and RF IC Design" (Wiley, 2006). He is the author and co-author of more than 250 scientific papers and has contributed to numerous conference presentations and advanced engineering courses.
He is an individual member of the Swiss Academy of Engineering Sciences (SATW). He has been member of several technical program committees, including International Solid-State Circuits Conference (ISSCC) and European Solid-State Circuits Conference (ESSCIRC). He is the General Co-chair of the ESSDERC-ESSCIRC conference that was held in Lausanne in September 2016. He has also served as a vice-chair for the 2000 International Symposium on Low Power Electronics and Design (ISLPED), exhibit chair for the 2000 International Symposium on Circuits and Systems (ISCAS) and chair of the technical program committee for the 2006 European Solid-State Circuits Conference (ESSCIRC). He has been an elected member of the IEEE Solid-State Circuits Society (SSCS) Administrative Commmittee (AdCom) from 2012 to 2014. He is also the Chair of the IEEE Solid-State Chapter of West Switzerland.
In this talk we will present some recent results achieved in our lab in the field of low-noise CIS. We will start with a review of fundamental noise mechanisms found in 4 transistors (4T) pixels based on pinned photodiodes (PPD) and the associated readout chain circuits showing that the noise coming from the readout electronics is dominant. After a detailed noise analysis of the whole chain, different noise reduction techniques are identified. Among these techniques, it is proposed to replace the traditional in-pixel thick oxide amplifying transistor with a thin oxide device for achieving minimum 1/f noise. This technique was evaluated in a first test chip designed in a 180 nm CIS process and embedding optimized readout chains exploiting the new pixels together with state-of-the-art 4T pixels optimized at process level for low 1/f noise. A mean input-referred noise of 0.4 erms was measured demonstrating a factor two reduction compared to the state-of-the-art pixels. A full VGA imager including a 4T pixel of 6.5 µm pitch with a properly sized and biased thin oxide PMOS source follower was then integrated in the same standard CIS process. The imager features an input-referred noise histogram from 0.25 e-rms to a few erms peaking at 0.48 erms at room temperature. This sub-0.5 erms noise performance is obtained with a full well capacity of 6400 e and a frame rate that can go up to 80 fps. The VGA imager also features a fixed pattern noise as low as 0.77%, a lag of 0.1% and a dark current of 5.6 e/s.
The integrated chip used a simple correlated double sampling (CDS) noise reduction technique. We will show that further noise reduction can be achieved thanks to correlated multiple sampling (CMS) using very energy- and area-efficient passive switched-capacitor circuits. We will finish by looking at how CMOS technology scaling can help to further reduce the input-referred noise, potentially bringing it close to or even below the photoelectron counting limit.
Bio: Christian Enz, PhD, Swiss Federal Institute of Technology (EPFL), 1989. He is currently full Professor at EPFL and Director of the Institute of Microengineering (IMT) and head of the IC Lab. He is also the manager of the EPFL site at Microcity in Neuchâtel. Until April 2013 he was VP at the Swiss Center for Electronics and Microtechnology (CSEM) in Neuchâtel, Switzerland where he was heading the Integrated and Wireless Systems Division. Prior to joining the CSEM, he was Principal Senior Engineer at Conexant (formerly Rockwell Semiconductor Systems), Newport Beach, CA, where he was responsible for the modeling and characterization of MOS transistors for RF applications.
From 1992 to 1997, he was an Assistant Professor at EPFL, working in the field of low-power analog CMOS IC design and device modeling. In 1989 he was one of the founders of Smart Silicon Systems S.A. (S3), where he developed several low-noise and low-power ICs, mainly for high energy physics application at CERN. His technical interests and expertise are in the field of ultralow-power analog and RF IC design, wireless sensor networks and semiconductor device modeling. Together with E. Vittoz and F. Krummenacher he is the developer of the EKV MOS transistor model and the author of the book "Charge-Based MOS Transistor Modeling - The EKV Model for Low-Power and RF IC Design" (Wiley, 2006). He is the author and co-author of more than 250 scientific papers and has contributed to numerous conference presentations and advanced engineering courses.
He is an individual member of the Swiss Academy of Engineering Sciences (SATW). He has been member of several technical program committees, including International Solid-State Circuits Conference (ISSCC) and European Solid-State Circuits Conference (ESSCIRC). He is the General Co-chair of the ESSDERC-ESSCIRC conference that was held in Lausanne in September 2016. He has also served as a vice-chair for the 2000 International Symposium on Low Power Electronics and Design (ISLPED), exhibit chair for the 2000 International Symposium on Circuits and Systems (ISCAS) and chair of the technical program committee for the 2006 European Solid-State Circuits Conference (ESSCIRC). He has been an elected member of the IEEE Solid-State Circuits Society (SSCS) Administrative Commmittee (AdCom) from 2012 to 2014. He is also the Chair of the IEEE Solid-State Chapter of West Switzerland.
Practical information
- General public
- Free
Organizer
- SCHOOL of ENGINEERING (STI) SEMINAR
Contact
- Loeffen Berthet Carole <[email protected]>