The Future of Nanoelectronics
Event details
| Date | 08.03.2010 |
| Hour | 16:15 |
| Speaker | Dr. Walter Riess, IBM Research, Switzerland |
| Location |
CE 4, Centre Est
|
| Category | Conferences - Seminars |
Scaling of semiconductor technology (CMOS) has been the driving force for the success of information technology. However, as device dimensions continue to shrink into the nanometer length-scale regime, conventional semiconductor technology will be approaching fundamental physical limits. New strategies, including the use of novel materials and 1D-device concepts, innovative device architectures, and smart integration schemes need to be explored and assessed. They are crucial to extend current capabilities and maintain momentum beyond the end of the technology roadmap time frame (post-CMOS era.
In this talk I will give a brief introduction into CMOS scaling, I will present its limitations and show routes towards the ultimate switch including the use of III-V materials and novel device concepts such as Impact ionization MOSFETs and in particular the tunnel FET.
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Practical information
- General public
- Free