Reliability of Wave Pipelining for NoC and FPGA
Event details
| Date | 19.06.2009 |
| Hour | 15:15 |
| Speaker | Prof. Guy Lemieux, University of British Columbia, Canada |
| Location | |
| Category | Conferences - Seminars |
Networks-on-Chip and FPGAs both require a programmable interconnect structure where high-bandwidth, low-latency communication is key to performance. Wave pipelining meets this requirement -- by sending data in waves through a logic network, and carefully timing the release of new data, maximum bandwidth and minimum latency can be achieved when everything is ideal. However, the real world is never ideal. Noise sources and unpredictable timing variation leads to serious performance degradation of wave-pipelined circuits. Accounting for noise, we will show that traditional synchronous circuits with registers offer higher bandwidth and are more reliable than wave pipelining. However, reliability and bandwidth can be improved by compensating for the main source of non-ideality, accumulated timing jitter, through the use of surfing and distributed asynchronous FIFOs. To estimate reliability of these circuits, we have devised new techniques based upon statistical timing.
Prof. Lemieux's homepage
Practical information
- General public
- Free